DRAM cell operation_ problem with the working

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legendkiller

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So I have a DRAM cell simulated. I understand we are not to raise the word line when the column line is low since there is no need for that. But shouldn't the capacitor be discharging when the gate voltage is low? why is it at about 750mV when the gate voltage is low and the source is high?

 
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You see the MOSFET substrate diode in forward bias, due to unsuitable transistor connection.
 

Sorry i did not get u.....
I think u were asking me to ground the body. i did that and i still get about 400 mV passing through....
 

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