Doubts in Understanding De-serialization of data

[anandkumarcr]

Hi there

I had a doubt in understanding the deserializer functioning :-

Consider a situation where I have a parallel data of 10 bits from a source which is running at 10Mhz which needs to be serialized and my receiver board(read FPGA) has a core clock frequency of 50Mhz.

My understanding is as follows :-
-> The 10-bit parallel data at 10 MHz is serialized by a serializer to send the data out at 100Mhz(10 bit parallel data x 10 MHz) serial stream.
-> I assumed we get a reference clock from the source of 100 MHz from the source in addition with the serial data stream.
-> I need to build a deserializer based on the above 2 data lines.

But a few doubts have started to creep in about my understanding :-

-> The reference clock that I get from a serial source - is it a 100Mhz clock or a 10Mhz clock in the above case ?
-> If it is 10Mhz clock that I am getting, and my board's clock frequency is 50Mhz, how do I generate 100Mhz clock or even worse (100Mhz x 2) for deserializing the data ?

Kindly let me know if my understanding is correct about the scenario of receiving serialized data stream.

Thank you and regards

 

[qieda]

Hi,

your understanding is correct.
For the deserialization you need a synchronous reference bit clock. In your system you need this 100MHz clock, which is synchrounous to your bit data rate.
Where you get this clock depends on your system
either you get it directly from the source (than you may need some delay for correct sampling)
or get a divided clock from the source (then you need a PLL to multiply this clock into your bit rate, plus maybe some delay)
or you recover the bitclock with a Clock Data Revocery (CDR) from the bitstream (this gives some requirements to the toggle rate of your bitstream)

A second way would be to have a higher clock to do an oversampling of you incomming data.
Maybe you need a PLL to get this higher clock.
This as similar to a CDR, because you also need some ways to detect the phase and bitrate of your serial data stream (e.g. a difined toggle rate so that you can align to the bit edges)

hope this helps

best regards

 

[treqer]

xilinx xapp866.pdf

 

[imbichie]

Hi,

If you are passing the 10Mhz clock from the source to destination then, you need the sampling clock frequency at the destination side as 100Mhz.

If you are passing the 100Mhz clock from the source to destination then, you can use the same clock as sampling, but the thing is that the passing 100Mhz must be a phase shifted version of the source clock(100 Mhz with some phase shift of 22.5 or something).

 

[treqer]

something like this. In practice, to adjust the phase of the type used by sending AAhex or 55hex. delay at the receiver picked in the middle of the reception of sustainable

 

[anandkumarcr]

Hi qieda, treqer and imbichie.
Thank you for making things clearer for me. Thank you