doubts in digital design concepts

Hi All,

I am facing difficulty in understanding certain concepts.
Could you please clarify my following doubts:

1) Is there any example of having an intentional combo loop in design? Can combo loops be useful? How does synthesis tool and gate level simulation act on combo loop. How do we meet timings of combo loops?

2) How do we meet timings of mux? Do we need to do setcase analysis at all select inputs of mux or does synthesis tool do it for us?

3) Can we have useful latches in our design? Can we use it at any other place than during DFT?

4) The latch borrowing concept...i see it written that it is for fixing hold problems. Latch borrowing is done to increase the sampling time to half clock period, then how does it fix the hold issue? Doesnt it mean increasing the time for setup?
The latch borrowing concept that i have seen is wrt sync clocks with different skews. Is there an example for latch borrowing for async clocks?

5) How can we generate a divide by 3 clock without using negedge flop. I thought i can put an inverter on the clock and then use the inverted clock further. But can we put an inverter on the clock while writing rtl? I thought we should not touch clocks at all in our design except for gating them.

6) How do we implement 4 deep fifo using f/f? :sad:

7) Is the reset recovery and removal time only for flops with async resets with sync deassertion or is it for reset synchronizer flops as well? How do we take care of metastability in async flops?

8) I think we cannot have a totally glitchfree circuit. So what do we do to meet the timing. If I have a glitchy logic which meets the timing, is it ok? Can i live with such a design or is there a probability that my circuit my go into metastability anytime?

Hi,
Your questions are deep and refers to several aspect of hdl and logic design, also answering whole question briefly is equivalent of writing a digital design book, so I think every one choose one question to be answered or discussed. I choose question 5.
5. Short answer is yes.you can gate clock in any order in Hdl, but if you aimed to implement your code in specific FPGA or cpld then you must take into account your target feature for clocking.
However,sourcing clock from combitional circuit is not good design practice.instead of using combitional logic for clock one can use for example DCM in xilinix's products.
Regards

Miralipoor, I think the OP was posting questions from homework or perhaps a take home exam of some sort. That is the primary reason I didn't respond to any of their questions.

hi ads-ee,
No they are not from my homework :smile:
I am studying and trying to learn digital design concepts at my own.
I am referring to many books, blogs and sites to grab this basic understanding.
Apart from certain rtl coding doubts, which i could resolve at my own, I was facing issues in understanding certain concepts, hence i posted it here :smile:

- - - updated - - -

Hi Miralipoor,
Thanks a lot for your reply.
I know that we use inverters and buffers during CTS but i wasnt sure if we can put logic on clock in design as well.
Your reply clears my doubt.

Hi shainky
I am sorry, I am agree with ads-ee.
Regards

got the answer of 6).

answer of 1)
https://asicdigitaldesign.wordpress.com/2008/03/07/cyclic-combinational-circuits/

Here is your answers -

1) Is there any example of having an intentional combo loop in design? Can combo loops be useful? How does synthesis tool and gate level simulation act on combo loop. How do we meet timings of combo loops?

[RJ] - Combo loop make design unstable, there could be numerous issue like race condition , circuit overheating , worst power consumption , as you know digital gates having few ps delay and if you have combo loop, it may toggle like anything and burn your circuit. I dont see any thing useful coming out of it.

2) How do we meet timings of mux? Do we need to do setcase analysis at all select inputs of mux or does synthesis tool do it for us?
[RJ] if you are analyzing design in different modes where your mux need to set properly , then u will have to use SCA , one example is function mode and test mode.
other couls be , normal functional mode , loopback mode, etc
If you dont give any SCA on Mux , synthesis tool will take care all paths combinations.

3) Can we have useful latches in our design? Can we use it at any other place than during DFT?
[RJ] Answer is Yes , latches are faster than flops and more power saving , but one have to extra careful while doing timing analysis.

4) The latch borrowing concept...i see it written that it is for fixing hold problems. Latch borrowing is done to increase the sampling time to half clock period, then how does it fix the hold issue? Doesnt it mean increasing the time for setup?
The latch borrowing concept that i have seen is wrt sync clocks with different skews. Is there an example for latch borrowing for async clocks?

[RJ] Latches borrow half clock cycles .. i cant explain it in detail here .. sorry for that.

5) How can we generate a divide by 3 clock without using negedge flop. I thought i can put an inverter on the clock and then use the inverted clock further. But can we put an inverter on the clock while writing rtl? I thought we should not touch clocks at all in our design except for gating them.
[RJ] You can very well generate , but you wont be having 50% duty cycle. it will be 60/40% duty cycle. Using gates are more dangerous than using negedge flops ,gates will give you glitch on clock ... this is more dangerous.




6) How do we implement 4 deep fifo using f/f?
[RJ] you can , you need to implement pointer logic.

7) Is the reset recovery and removal time only for flops with async resets with sync deassertion or is it for reset synchronizer flops as well? How do we take care of metastability in async flops?
[RJ] reset removal and recovery is same as setup/hold time check , for reset synchronizer, there is no need to check timing on that , those are build to take care metastability due to reset violation ..thats why those called "reset synchronizers "

8) I think we cannot have a totally glitchfree circuit. So what do we do to meet the timing. If I have a glitchy logic which meets the timing, is it ok? Can i live with such a design or is there a probability that my circuit my go into metastability anytime?
[RJ] You can have, glitch come in picture only due to combo logic or different clock domain. If you use sync cell properly and flopped your signals carefully, your design will be glitchfree.


By the way ... Good questions, you have gone much deeper in digital design.