san2004
Member level 1
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Hi,
Currently I am working on one multilayer board (4 layers) in which I have to give provision for Bed Of nails tester. I understood that I have to add via for each net & that will be used for in-circuit testing.
But still I am not clear.. so my question is what precaution I have to take as PCB Designer for bed of nails tester ( settings, routing etc.) & I want to know the basics of DFT audit .I just know that dft means design for test .
Thanks in advance.
Currently I am working on one multilayer board (4 layers) in which I have to give provision for Bed Of nails tester. I understood that I have to add via for each net & that will be used for in-circuit testing.
But still I am not clear.. so my question is what precaution I have to take as PCB Designer for bed of nails tester ( settings, routing etc.) & I want to know the basics of DFT audit .I just know that dft means design for test .
Thanks in advance.