Doubts about the range of input signal of ADC

[kickbeer]

i have just read some article about analog-to-digital converter. i'm confused with the range of analog input signal for example 1.4Vpp. does it mean from -0.7 V to + 0.7 V peak to peak?

 

[engr_najam]

signal to adc

in ADC it may be from 0 to 1.4 volts too, as in binary conversion normally the signal is made complete positive by adding offset voltage.

e.g ur voltage can be made by
0.7 + 0.7*sin(t).

 

[kickbeer]

offset signal for adc

thx..in a flash or folding ADC..so the voltage references generated by resistor ladder must be in the postive range of 1.4Vpp??

 

[RFDE]

analog signal peak to peak input adc

if you use a differential architecture , then it means from -0.7 to 0.7 , i.e. Vref+=0.7 & Vref-=-0.7

 

[kickbeer]

differential signal to adc

if you use a differential architecture , then it means from -0.7 to 0.7 , i.e. Vref+=0.7 & Vref-=-0.7

how a differential architecture look like? and u said from -0.7 to +0.7, what if, for instance, input level is 0 and this is conected to a gate of transistor?? I'm bit confused since the tranistor will be off because the threshold voltage is not exceeded. How to overcome this?

 

[amriths04]

biasing input to adc

It just means that the input voltage range is 1.4V. The absolute minimum and maximum values depend on the input common-mode voltage about which your circuit is biased.

For example if in a single-ended (or differential) configuration, having a single power supply, if you have a input common mode of say, 0.9V, then, your input signal will swing from 0.9-0.7V to 0.9+0.7V.

If it is mentioned as differential peak-to-peak, your signal will swing from 0.9-0.35V to 0.9+0.35V in one of the differential inputs and would be antiphase in the other differential input.

Hope this helps.

 

[kickbeer]

differential input voltage for adc

It just means that the input voltage range is 1.4V. The absolute minimum and maximum values depend on the input common-mode voltage about which your circuit is biased.

For example if in a single-ended (or differential) configuration, having a single power supply, if you have a input common mode of say, 0.9V, then, your input signal will swing from 0.9-0.7V to 0.9+0.7V.

If it is mentioned as differential peak-to-peak, your signal will swing from 0.9-0.35V to 0.9+0.35V in one of the differential inputs and would be antiphase in the other differential input.

Hope this helps.

It's still not clear. Can we read the common-mode voltage through simulation? Is the common-mode voltage appearing on both gate of transistor?

 

[amriths04]

differential input to the adc

Yes, a common-mode voltage is a DC voltage that is used to bias a transistor, so that it operates in saturation. So the same common mode voltage appears at both the inputs. Your signal would be riding on it.

 

[kickbeer]

adc add dc offset to input

Yes, a common-mode voltage is a DC voltage that is used to bias a transistor, so that it operates in saturation. So the same common mode voltage appears at both the inputs. Your signal would be riding on it.

i almost understand but when a input voltage is in sinusoidal and there is no offset on that that voltage, from what i simulated(DC operating point), the DC operating point is 0 V. That means the only way to bias it, is adding an DC offset to the input signal in order the transistor operate in saturation. Is that what you mean? Or we bias it on other way??

 

[amriths04]

adding 0.7 v to a signal

you are exactly right.

 

[lajeffo]

input signal for adc single ended

hello,
still not understand, if there is a 5v vref what would b the bit pattern for 2v input voltage

 

[kickbeer]

input signal of adc + amriths04

hello, Vref must cover the whole input of ADC