master_picengineer
Banned
Hi all,
I have some question and I hope you help me.
While studying the PFD (2dff+ and gate) , i found that the dffs resets when CLK1 and CLK2 are sets. At this moment the CP (composed of a PMOS and a NMOS transistor) has both PMOS and and NMOS on and there is a short circuit.
1- Is there a possibility to hurt the CP at that moment (Transistor burning) ?
2- I there another better better CP shematics that take into account this pb ?
Thanks in advance for your participation.
I have some question and I hope you help me.
While studying the PFD (2dff+ and gate) , i found that the dffs resets when CLK1 and CLK2 are sets. At this moment the CP (composed of a PMOS and a NMOS transistor) has both PMOS and and NMOS on and there is a short circuit.
1- Is there a possibility to hurt the CP at that moment (Transistor burning) ?
2- I there another better better CP shematics that take into account this pb ?
Thanks in advance for your participation.