doubt on a delay insertion

[nsreekanthbabu]

hi,
i am unable to realise correct functionality diffrence in the below expressions,

#10 a <= b;

and

a <= #10 b;

i guess in both cases, b value is assigned to a after 10 time units.
please help me out.

regards,
sree

 

[Davood Amerion]

#10 a<=b
means wait for 10 unit of time (ie ns)
then get 'b' value and put it to 'a'
whereas
a <= #10 b
means get 'b' value (in zero time) and put it to 'a' after 10 unit of time

 

[Nir Dahan]

Take a look at this paper http://www.sunburst-design.com/papers/CummingsHDLCON1999_BehavioralDelays_Rev1_1.pdf

it will give you a pretty good idea on delays in verilog - it has nice diagrams too.

ND.

http://asicdigitaldesign.wordpress.com/

 

[risccpu]

The above paper is very helpful.