Doubt in VHDL Process statement

Status
Not open for further replies.
R

revooridinesh

Member level 1
Joined
May 31, 2010
Messages
41
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
Canada
Visit site
Activity points
1,553
Hi

Process(clock)
begin
---
---
---
end process

How to know how much time the above three statements takes to execute ? Because the time they take should be less than half cycle period in order all 3 statements to be executed in one clock change.

Thanks
 

VHDL is not a programming language. a process executes in 0 time. It will map to logic. So your process will only execute when the clock signal changes.
 

VHDL statements don't take "time to execute" because in the generally case each statement describes independent hardware elements, e.g. registers and combinational logic.

The delay between registers or in- and outputs in a particular data path has to be considered however. VHDL synthesis tools perform timing analysis to guarantee correct operation according to specifications.
 

Thanks Tricky and FvM
Got the point
Do you know any good material where I can study timing analysis in Xilinx.
 
Last edited:

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…