[SOLVED] Doubt in Verilog module instantiation.. Help Me please....

module MUL_FOUR(A,B,P);
input [3:0]A;
input [3:0]B;
output [7:0]P;
reg [3:0]s1,s2,s3,s4,s5;
reg c1,c2,c3,s6;
parameter zero=0;

MUL_TWO M1((A.A[1:0]),
			(B.B[1:0]),
			P.s1[3:0]);

MUL_TWO M2((A.A[3:2]),
			(B.B[1:0]),
			P.s2[3:0]);
			
MUL_TWO M3((A.A[1:0]),
			(B.B[3:2]),
			P.s3[3:0]);

MUL_TWO M4((A.A[3:2]),
			(B.B[3:2]),
			P.s4[3:0]);

RCAF A1((a[1:0].s2[1:0]),(a[3:2].s2[3:2]),
			(b[1:0].s3[1:0]),(b[3:2].s3[3:2]),
			(s.s5),
			(cout.c1));

RCAF A2((a[1:0].s1[3:2]),(a[3:2].s4[1:0]),
			(b.s5),
			(s.p[5:2]),
			(cout.c2));

HA HA1(c1,c2,s6,c3);

RCAF A3((a_l[0].s6),(a[0].c3),(a[1].zero),(a[2].zero),a[3].zero,
			(b[0].s4[2]),(b[1].s4[3]),(b[2].zero),(b[3].zero),
			(s[0].P[6]), (s[1].P[7]),GND);


endmodule


// sub module

module RCAF(a_l,a_h,b_l,b_h,s,cout);

input [1:0] a_l,a_h, b_l,b_h;  
output [3:0] s;   
output cout;     
wire c1,c2,c3;

FA FA0(a_l[0], b_l[0], 1'b0, s[0], c1);
FA FA1(a_l[1], b_l[1], c1, s[1], c2);
FA FA2(a_h[0], b_h[0], c2, s[2], c3);
FA FA3(a_h[1], b_h[1], c3, s[3], Cout);

endmodule