Doubt in Synchronizer

metastability synchronization chain

Hi Friends ..
I am having doubt related with dual flop synchronizer ...
My doubt is that suppose data came at input of first flop is '1' and metastability occurs at first flop than suppose our output of 1st flop is settled to zero( (output becomes stable before arrival of next clock edge ) than second flop will give output zero ( u got '0' at output of synchronizer ) but input supplied to synchronizer was '1' so you will get wrong value ... Which is not desired ...

This type problem can create wrong functionality of the circuit ....
If I am wrong correct me ....

So how to handle this type of problems in synchronizer ...

Regards..

Hi Udit,

You are right , with the synchronizer flop actual arrival of of synchro async signal may vary 2 or 3 clock cycles. By means of synchronizer we just prevent the metastability for further propagation but this cycle shift can not be prevented.

Here designer has to make sure his design works correctly even if there is 1 cycle additional delay in synchronization. :|

But if you notice for most of the async signals it does not matter e.g. reset or interrupt.
I hope this will help

Hi Sameer,

There is any technique to sure that whatever data was provided to input of synchronizer , you got same data ,if there is a data mismatch than it will notify .....

Beacuse this mismatch can create Problem if transfered signal is a control signal than design will not work properly
I am having no problem of additional delay but I wants to make sure that data transfer correctly ..

Regards

Hi Udit,

I don't think there is any method because the probability of signal arrival is totally random in this case.
But can you explain what kind of problem do you foresee in this case ?
Your input is async in this case you have to just assume you are getting async signal either at nth or N+1 th cycle. This assumption is fare enough in case of async signal.
I would again like to emphasize correct logic anyway will reach to the circuit after 1 clock.
:|

Hi Udit,

Think of it in this way, you are transferring a change across synchronizer, and when that change arrives is uncertain by 2-3 cycles.
Say if signal was initially at 0, and change the input to synchronizer to 1, now the output of synchronizer may still remain at 0 for another 2-3 cycles, or may see 1, thats the uncertainity. But you do get a 1, sooner or later.
So what is the mismatch you are talking about ?

Hi all
As told rjainv and Sameer that synchronizer will give correct output after some clock cycle .....
But suppose this synchronization signal is changed after one clock cycle(reading clock) so than synchronizer will missed that data input ...... So how to avoid this Problem ....

I am thinking One Circuit for checking that the transfered value is correct or not and as well as there is less chances of going output into metastable state(signal will pass thru three flip flop) ,
As I am thinking that there is less chance of going both synchronization chain into metastable state ..

Take two Synchronizer (Dual Flop)
Input to 1st synchronizer is Whatever signal want to transfer ..
Input to 2nd synchronizer is inverted of Whatever signal want to transfer ..
Put XOR gate at Output of Both synchronizer ... (Say output of XOR is OP_XOR)
Now Take D Flip FLop ..Input to this is Output of 1st Synchronizer ...and OP_XOR is used as Enable signal ....Which will Enabled Only whenever Sampled value is correct from both Synchronizer else it will not enable ..
and also OP_XOR can be used for conforming that input to synchronizer is sampled correctly or not .........
Is any Problem in this Circuit ? Please comment on this ........


Regards

Hi Udit,

suppose this synchronization signal is changed after one clock cycle(reading clock) so than synchronizer will missed that data input ......

Click to expand...

As long as pulse width of asyn signal is greater than 1 clock + setup time of FF the normal synchronizer works properly.In most of the cases this is kept as 1.5 clock pulse duration.
If this is not the case I think the circuit you mentioned also will miss the pulse at first flop itself.
I hope I am clear..

Hi Sameer,
But if this synchronizer signal is changed after 2 clock cycle than also there is chances because if at first clock it did't sample (means went into metastable state and sattled into oppsite value )and at second clock pulse this signal changes and any time violation occurs than also there is chances of not sampling correctly......

as i m thinking my circuit will also having same Problem but it can inform that any sample is missed .......... So according to that furthur action can may take place ...
Is its correct ??

Please comment on this ....

Regards