Sasi Cm
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Doubt in port mapping:
How to port map the following module in Verilog. The encoder has the input as x[120:0] and output as y[55:0]. Now the decoder obtain the input from encoder by port mapping. The decoder has the input as a[55:0] and output as b[125:0].
Now how to port map the y and b.
How to port map the following module in Verilog. The encoder has the input as x[120:0] and output as y[55:0]. Now the decoder obtain the input from encoder by port mapping. The decoder has the input as a[55:0] and output as b[125:0].
Now how to port map the y and b.