Doubt in blocking and non blocking

[marihari]

I am new to the system verilog. Blocking statements can be used for combinational circuits and non blocking statements can be used for sequential circuits. But i don't know the reason behind using the use blocking and non blocking. Please help me.

 

[babaduredi]

If you understand operation of sequential and combinational circuits, explanation of blocking and non-blocking is self-explanatory. In sequential circuits, we just want outputs of many memory elements(flops, registers) to be updated simultaneously on valid clk edge, so non-blocking assignments are required.

In combinational circuits, assignments have dependency on previous assignments. So next instruction executes after current one and execution takes place in same way as control passes in high level languages such as C/C++.

 

[marihari]

If you understand operation of sequential and combinational circuits, explanation of blocking and non-blocking is self-explanatory. In sequential circuits, we just want outputs of many memory elements(flops, registers) to be updated simultaneously on valid clk edge, so non-blocking assignments are required.

In combinational circuits, assignments have dependency on previous assignments. So next instruction executes after current one and execution takes place in same way as control passes in high level languages such as C/C++.

Thanks for your valuable reply

 

[naught]

I intentionally try to avoid using the blocking expression"=".
actually the "<=" could do all your work, both combinational and sequential circuits.

sequential
always@(posedge clk)
begin
a<=b;
end


combination
always@(b)
begin
a<=b;
end

 

[babaduredi]

I intentionally try to avoid using the blocking expression"=".
actually the "<=" could do all your work, both combinational and sequential circuits.

Hi Naught,
what if there is a combinational logic using a as input. suppose there is another logic to be defined as c=a AND b;
than you will end up in unnecessary always blocks with race conditions on c, leading to momentarily corrupt values in c(spikes). Another important thing i want to mention here the way execution take place of always. If constraints are same, execution take place randomly. So it's highly recommended practice to design combinational logic using blocking assignments.
Do you synthesize the logic you design in this manner?

 

[naught]

I checked the verilog syntax book, sorry I confused VHDL with verilog. Your way is better.

could you please explain a little more about "If constraints are same, execution take place randomly."?

 

[babaduredi]

could you please explain a little more about "If constraints are same, execution take place randomly."?

Suppose there are 2 or more always with similar conditions(same time edges) :
always @(posedge clk or posedge rst)
if (rst) y1 = 0; // reset
else y1 = y2;

always @(posedge clk or posedge rst)
if (rst) y2 = 1; // preset
else y2 = y1;

Then order of execution of these always blocks is unknown. Suppose after reset, first always executes first, both y1, y2 will take value 1 and if second always executes first after reset, both y1, y2 will take value 0, leading to race condition.

 

[naught]

good example. Thanks.

and obviously one shall avoid designing a logic in this way.

 

[rocking_vlsi]

But still people does mix both blocking and non-blocking statements.

as
always@(posedge(clk))
begin
temp_var=a&b;
if(condition)
temp_reg<=temp_var;
end

For simulation and synthesis how does it differ?

 

[FvM]

As far as shown, it's legal Verilog code that doesn't cause simulation to synthesis mismatch.

For problematic usage of non-blocking statements, review the "classical" cummings paper http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf