Does this SCL behavior seriously affect the I2C address setting/communication?

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Sunnyback

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Hi,
:thumbsup:
I'm using a TLV493D with a power separated by FET from microcontroller power, like Slave #1 in figure 14 of I2C interface note.

Sometimes my few TLVs return NCK and cannot recover even turn on/off by IO_0 pin.
A difference between the note and my project is SCL pin is high during 200us of after power on by getting IO_0 high.

Does this SCL behavior seriously affect the I2C address setting/communication?

I'm feeling strange since many of my TLVs are successfully work but this happens with few chips beside low frequency.

Here is the schematics:



The timing of I2C bus:



Also, I tried getting SCL low during the configuration phase, however, some chips still return NCK sometimes.

 

Your measurements don't show how the slave device is locking the bus.

Why SDA is low in the waveforms? Is it intentionally pulled low by the master or irregularly by the slave?

A slave may pull down SDA if it's caught in the middle of a read operation. In this case, the slave should perform the recover procedure according to Philips/NXP AN10216-01.

 

Hmm...that makes sense, thanks for the info, will check it out.
And i found "General Reset" command that sends 0x00 to SDA but Is this effective for all time in irrespective of internal state?
I mean, Is there any non-volatile area or register and no possibility to inhibit resetting?
 

Hi,

As I understand it this is not a full device Reset, it is just (method for) an I2C interface Reset....

Klaus
 

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