Does this design need a FIFO Synchronizer ?

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elec-eng

elec-eng

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synchronizer same clock

Hi all

Could you please help me

I have a design at which multiple synchronous clocks are used "as depicted in the picture"

So I have the case of "Synchronous Clock Dominn Crossing" , i.e the clocks have the following properties:

-They are derived clocks " i.e they are from the same root clock"

-Each clock is an integer multiple of the root clock

-All positive-going edges of all clocks are alligned

So, Does I have to use synchronizers "2 Flip-Flops or FIFO" between different

sunsystems using these synchronous clocks





thanks
 

When you say that they are derived from the same clock and that the positive edges are guaranteed to be aligned, do you mean that they arrive at the FPGA like that, or that they are guaranteed to arrive at the sampling flip flops like that?

If these clocks start out aligned, but are distributed by different clock trees, there is no guarantee that they will stay aligned.

So, if you know for a fact that these clocks arrive at the sampling block aligned, you could probably dispense with metastability hardening. If you can afford the extra timing hit though, it is better to be safe than sorry and sample them.

r.b.
 

Hi,

There are different possibilities here like,
- If both clocks are derived from same source and both are in phase, u need not to synchronize.
- If both clocks are same and with fixed phase shift, then u need not synchronize
- If source clock is faster than the destination clock u may have to check for the data stability, i.e. u have to make sure that the data is effectively latched by the destination.. this u can do by enable based synchronization.
Hope this will help u

- Keshav

Added after 3 minutes:


i will be able to expain more if i could see the figure

- Keshav
 

I suppose you derive these clocks from one source using a PLL in the logic chip? Some design tools (at least for FPGA for the @ltera company) will guarantee (or point out the problem) that it will work without synchronisation flops.
 

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