bittware
Full Member level 4
Hello gurus,
In FPGA design, does the Static Timing Analysis(STA) help to reduce functionals simulation test vetor quantity? I have read such statments in a lecture as"STA analyses all possible paths within a design which doing manually would take lot of time and effort." My question is whether functional simulation goal is to active all possible paths? If yes, how STA makes help? If no, can STA carry out the same work that only could be done by stimulating some certain functional simulation vectors?Additionally, I dont think all possible paths have meaning for my case. That is to say some paths will never be actived in real word, so in this case does the STA still make any sense?
Thanks for any prompt.
In FPGA design, does the Static Timing Analysis(STA) help to reduce functionals simulation test vetor quantity? I have read such statments in a lecture as"STA analyses all possible paths within a design which doing manually would take lot of time and effort." My question is whether functional simulation goal is to active all possible paths? If yes, how STA makes help? If no, can STA carry out the same work that only could be done by stimulating some certain functional simulation vectors?Additionally, I dont think all possible paths have meaning for my case. That is to say some paths will never be actived in real word, so in this case does the STA still make any sense?
Thanks for any prompt.