Specman is co-simulator, so, it works together with Verilog/VHDL simulators. Common usage of Specman is to have only Design Under Verification (plus wrapper) in HDL and complete Verification environment defined in e. Communication (in both direction) between Verification environment and DUV is done through Port objects in e and have big timming overhead (it is very slow, as any other cosimulation).
It is possible to access DUV internal signals in Specman, so there are no problems with generation of functional coverage items (of course if you have idea how to define them).
Theoretically, DUV can be design plus Test environment in Verilog (with some synchronization ports with Specman). But in this way we loose main benefits from using of Specman tool (like automatic random generation, ...). You still could use Functional Coverage, but you need to define functional coverage items (and it is everything else then rutine engineering job).
If idea was to make transition from classic verification approach to constraint random, functional coverage driven verification approach more easier, forget this. If you want to switch to Specman, it need to be right way from beginning, not to use some hibrid solution.
By the way, if you actually want only Functional Coverage feature, you could develop yourself something similar in your existing Verilog verification environment. You need to add assertion checkers into your code, and dump coverage items in files in appropriate format (don't forget to put time for cross-coverage purpose) and do post-processing of that files (Perl scripts) to extract Functional Coverage results. Actually it is the same principle how Specman do that, I mean. Of course it is better to have this automatically in the tool. This Functional Coverage feature looks extremelly simple to implement, I really don't know why RTL Simulator vendors don't have it for free in all version of their tools.