Does RtL design will contain flops ??

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sara1983

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Hello All,
Does RTL design will contain flip flops... or does the RTL synthesized netlist will only have flops... ?? Can you please elaborate.... ??

Thanks!
Satish
 

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@sara1983 ,
Does RTL design will contain flip flops...
-- An RTL has the description in a high level language(VHDL/Verilog) that represents the behavior of a flop.

or does the RTL synthesized netlist will only have flops... ??
-- Look up the definition of a "netlist"!

Search - "difference RTL and netlist"

I leave it as an exercise for you, the answers are easy to find out!
 

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