Does PIC16F18856 work if centre pad is left floating?

[treez]

Hello
We have got a prototype PCB made up and realise we forgot to connect the centre pad of the PIC16F18856 footprint to ground.
We are using the 6X6mm QFN type, shown on page 653 of the datasheet

Page 5 of the datasheet says that the centre pad should be connected to circuit ground, but it doesn’t say if the chip wont work if it the centre pad is not connected to ground. Do you know?

PIC16F18856 datasheet
https://ww1.microchip.com/downloads/en/DeviceDoc/PIC16LF18856-76-Data-Sheet-40001824D.pdf

 

[kripacharya]

Don't know for sure, but you will notice that wording in same page footnote#2 uses the word must be connected... , while note#3 says should be connected.

 

[FvM]

As a first step towards clarity, you can measure if the two VSS pins and center pad have low R connection.

Connecting as many VSS pins as available reduces ground bounce and EMI susceptibility and is thus recommended.

If no low R connection, it could be a matter of substrate grounding, different effects on analog circuit behavior.

 

[andre_luis]

Page 5 of the datasheet says that the centre pad should be connected to circuit ground, but it doesn’t say if the chip wont work if it the centre pad is not connected to ground

From my previous experience with another Microchip's relative of the PIC16F's family, even forgetting to route one of the side pins of a DIP package, this was enough for the microcontroller to not work, and likewise there were no mention in the datasheet of the redundancy of these GNDs or not, so if I were you, I would do all the grounding routing as much as possible, even for the sake of signal integrity internally to silicon, equalizing the internal electrical potential references; in the absence of an unambiguous statement of the obligation to connect this pad, I would read as mandatory. Another point to consider is that QFN packages, because they have no exposed leads, their total dissipation area are smaller, and therefore it should not be negleted that even though the internal pad were by assumption primarily designated for that purpose (in theory, only connected to the silicon substrate die), in the asic routing process, somehow the sizing of the internal grounding tracks could intentionally have took into account the use of this pad, just guessing.