Hi,
Datasheets for LM339 and LM2903, etc., group of comparators show simplified or quite complete schematics of internal structures: NPN open collector or NMOS open drain output.
LM339 output device is an NPN bjt, so a pull-up is necessary for the comparator's high-z output (when In+ < In-) to have a positive voltage.
Surely chancing a PD calculation as the reasoning for violating a voltage-limited device's voltage limit is wonky maths. For example, I'll bet you can't use a CD4000 or SN74xx at 100V and much less at 300V so long as you limit the current to a tiny amount.
When In+ > In-, the comparator will try to sink current by becoming a low impedance path to 'ground'. The internal open collector NPN will ideally only have (I_Rpull-up x R_ce) voltage across its emitter-collector - will that be what the datasheet says to expect (a few hundred mV at most) or will the 40V to 60V maximum Vce of the internal NPN get fried by trying to sink 300V?
Which begs the next question: If your idea works, and only a few mV to a few hundred mV develop across the internal NPN and no voltage spikes damage it, where will the other 299.9V disappear to, or not disappear?
Last, Schmitt triggers, whatever, bla bla bla, and the supposed confusion and a somewhat frivolous attitude - hysteresis, hysteresis, hysteresis... put some hysteresis on the comparators, it's easy to understand why, for God's sake, man! If you don't know what hysteresis is, here's a quick introduction:
Figures 3 and 4
Has a calculator and brief explanation