Hi,
There are two gate capacitors inside a FET.
One is from gate to source. It often is the larger one. This capacitor needs to be charged and discharged like an ordinary capacitor.
The ammount of charge is: Ugate x Cgs
The other - usually smaller one - if from gate to drain. On first sight one may imagine that the smaller capacitance may cause smaller ammount of gate charge charge. This is true as long as the voltage on drain is constant. But using a FET as a switch causes the drain voltage to change.
Imagine a FET as low side switch for a 24V valve. During switching the voltage on drain falls from 24V down to 0V. This charge (voltage multiplied with capacitance) you need to add to the usual calculation Ugate x Cgd. Now you get total gate charge:
Qt = Ugate x Cgs + Ugate x Cgd + Uds x Cgd.
The additional gate charge is exately in the time where the drain voltage moves (switching). And this slows down switching. Switching time increases and in the same ammount switching loss increases.
The additional gate charge is called "Miller effect". It is a main parameter with switching FETs, especially with high voltage switching.
Klaus