Does cadence RC tool support readmemb(file name, mem) construct?

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Sudharani

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I need to use readmemb to initialize RAM with default values.. With this construct, I m not able to proceed with ASiC synthesis.. So is there any alternative for this?
 

Readmemb is not a synthesisable key word.
You can not initialize a RAM instance in the synthesis tool.
The RAM instance should match a liberty description.

Only a RAM instance made with registers could be initialize with you need.
 
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can u post/ provide link where i can find the way to initialize RAM during ASIC/FPGA Synthesis?
 

There is two question in your sentence.
For ASIC, it s not possible to initialize the ram content.
For FPGA, you could define a file to preload the ram content, this is provide with the FPGA tool which you used to generate the memories model for the FPGA target.
 
Thanks for confirming that memory initialization not possible in ASIC synthesis...Actuallly memory(RAM instances) models are generated and instantiated in the source code itself... Now how to pass the default value file during synthesis?
 

Do you speak about FPGA synthesis?
If yes the ram model should have an attribut which indicate which file to read to preload the ram on the FPGA.
 

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