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The PMOS transistors in the upper circuit are biased as pull-up resistors in a string, with gate tied to ground, Vth to Vdd. Each string to a NMOS in the lower circuit. Vth tied Vdd is intended to minimise leakage current to the extreme. The string resistance is equal to 3.Ron(PMOS). This is different from the current mirror (active load) which consumes power.
PhD MSc DIC (Imperial College London) BEng(Hon) Manchester
You either quoted wrongly or you are seeing things.
I never said bulk is one of the 4 terminals. Look carefully at my previous post again, I only said Gate, Drain, Source and Threshold are the 4 terminals of MOS.
Can't you see the threshold terminal of the PMOS is connected to Vdd in the circuit?
It's threshold terminal. If you are not convinced, you can check IEEE standard symbols and any popular textbooks. You need a terminal to connect to bulk to bias the bulk for threshold voltage, this terminal is called threshold terminal.
Added after 52 minutes:
Perhaps the book you are using is Jan Rabaey's book, Bulk is your 4th terminal.
To me, Threshold or Body is the 4th terminal. Since it is a terminal that connects to body or bulk, it doesn't really matter.
The circuit above has the PMOS's threshold, body or bulk tied to Vdd, this is assumed knowledge just liks NMOS's body is tied to Ground.
To me, source-body or source-bulk voltage is threshold voltage Vth. The switching threshold voltage is VTn for NMOS, VTp for PMOS.
Your conventions could be different from mine.
Added after 3 minutes:
Perhaps you mistook my Vth as the switching threshold voltage VTn or VTp, which I would usually used in general VT, or VTp or VTn in specific.
Hi SkyHigh, maybe you are living in a completely different world -- we don't call the fourth terminal of MOS transistor as 'threshold'. It is called the 'bulk' here in the United States and many other places! I am sure over 90% of all the analog IC literatures would use this convention.
The circuit itself is a constant gm bias circuit, i.e. the bias current is determined by the aspect ratio of two NMOS transistors and the resistor.
To SkyHigh
I never say that you say the the 4 terminals are .... and bulk. Look at my centence clearly. I think most people use bulk for the 4th terminal. Your words just made me confused. Now I'v known our conventions are different and understood your meaning.
If the pmos are used as current mirrors, this circuit can serve as constant-gm biasing or ptat source. ie if the two nmos work in saturation region, it is a constant-gm circuit, refer to page 248-251 in "analog integrated circuits design" by Ken Martin. If the two nmos work in sub-threshold region. The I-V function of nmos is just like bipolar transistor(exponential relation) and it is a ptat source.
But here why use three series pmos? The top pmos are in triode region and can't consist current mirror.
this is a simple volatge reference.
all the pmos are always on, so the voltage in m7 drain is close to vdd. then setting the vref you set a refernce voltage at the output. r1 and r2 also form a resistive divider.
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