vGoodtimes
Advanced Member level 4
Just curious on everyone's opinion of numeric_std_unsigned in the recent VHDL2008 standard. The most cited reason against using std_logic_unsigned was its origin at synopsys, followed by concerns that the code would not be portable. Now that IEEE has recreated (and updated) the package, will the advice be to move to numeric_std, or numeric_std_unsigned?
numeric_std_unsigned.all gives a coding style that is similar to Verilog. At the same time, overloading "=" to have a numeric interpretation means a lack of size-mismatch warnings.
numeric_std_unsigned.all gives a coding style that is similar to Verilog. At the same time, overloading "=" to have a numeric interpretation means a lack of size-mismatch warnings.