spriteice
Junior Member level 2
How many of you actually declare a Function or a Procedure in VHDL?
For me, I only use Procedure for simulation.
Is it feasible to use function/procedure for synthesizable designs?
Maybe it's because I haven't done any functional verifcation design?
For me, I only use Procedure for simulation.
Is it feasible to use function/procedure for synthesizable designs?
Maybe it's because I haven't done any functional verifcation design?