What you have read are both correct!
1. In some designs, to be really safe, you will observe that the engineer has put placement constraints on such sync flops such that tool places them as near as possible. But I also have designs running on hardware without such constraints.
2. You should not put any type of combi logic at such paths. Do whatever you have to do with the signal after the sync is done.
As FvM says above, the tool will by default do all type of timing analysis on the paths.
Have you already run timing analysis? Do you have hold problems?
If not just do it and see the results (do not get too carried away by what can happen or might happen)!