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I assume that by read and write freq you mean the data rates at the read and write interfaces.
For both synchronous and asynchronous clocks you will need a FIFO.
Hi sharath666,
My question is, of the write clock frequency is 100mhz and read clock freq is 200Mhz. The data is written and read at 1 byte per cycle, do we still need a fifo in case 1) when clocks ate synchronous and 2) when clocks are async
but both frequencies don´t need to be sychronous with a FIFO.
Often a FIFO is used when an isochronous data stream (from ADC) is processed in packets (or vice versa).
This means .. for example:
an ADC samples with a constant frequency of 10.000 samples/second. every 100us new data are received. (mind: input to FIFO with 10.000 samples/second)
if you need to process the data evry 100ms, then you may wait 90ms without reading data and within the next 10ms you can (or must) read 1000 sample data as bulk.
(Here the FIFO output data rate is max. 1000 samples/10ms = 100.000 samples/second max, but it averaged it must meet the 10.000 samples/second of input data rate)
I think by synchronous and asynchronous you mean in phase and out of phase. se
If the clocks are in phase and of the same freq, you don't need a FIFO.
If the clocks are out of phase (irrespective of whether they have the same freq or not) you have to use a FIFO.
As i said, my read freq is 200Mhz and write freq is 100Mhz. and bytes are written and read at 1 byte per cycle. Cant we work with just a synchronized enable signal which will enable read at every second cycle? why do i really need a fifo?
i think you have different cases:
1-same frequency and both clock are synchronous --> no need to any type of synchronization but you may need fifo depending upon requirnment.
2-same frequency and asynchronous --> you my need to use synchronization circuit which is a simple 2 or 3 flip flops.
3-different frequency:
a-if the two frequencies are doubled or have this relation f1 = (2^n)*f2 ,n =1,2,3,... and synchronous--> then you may need to use synchronization circuit and try to adjust the receiver that what will read for n-clock cycle is the same data.
b-if they are the two frequencies are not related or asynchronous --> here you may use either hand shacking synchronizer or asynchronous FIFO depending upon: burst mood ,read and write rate.
Hi Shainky. If you can guarantee me that both the clocks are phase aligned and they will continue to be phase aligned till as long as the circuit is in operation, then you don't need a FIFO. As you say, you can read every alternate clock.
how would we determine the depth of fifo in that case? Taking the same example,
"my read freq is 200Mhz and write freq is 100Mhz. and bytes are written and read at 1 byte per cycle." A burst of say 8 bytes is the max load that can come on the write side.
Can i just work with a two deep fifo?
If they are truly synchronous clocks then you can get away with no FIFO. You are writing 8 bytes at 100 MHz, but only need to read every other clock cycle. If they are asynchronous then you need to compensate for the clock domain crossing, and the number of entries in the FIFO depends entirely on the synchronizer depth and when the signal(s) crossing between the clock domains are sampled.
thanks ads-ee.
I was looking for depth of fifo in asycn clock cases when read freq> write freq.
Because the read is happening more often and we want fifo only for synchronization, i think 2 deep fifo should do, " irrespective of the read/write freq value". This is my assumption. I am not sure about this number, so seeking help on the same.
You will need more than 2 to guarantee operation. It's dependent on the frequencies and the pattern of reads and writes that are occurring. Even if the pattern is evenly spaced the synchronizers between the clock domains will require more than 2.
If at each 100MHz a byte is written, and at each 200MHz a byte is read (tried to be read because the writter could not provided enough data!)
If synchronous clock, nothing to do
If asynchronous clock, a ready signal from 100MHz domain need to be synchronize in the 200MHz domain to indicate a new byte is valid.
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