Do we have to meet max fanout constraint ?

[pavanks]

Hi,

If i meet the max cap and max trans constraint and have some max fanout violations.
Can i ignore those ?

Normally they say max fanout is a soft constraint why ?
Isn't the max fanout constraint also in the standard lib file?

Thanks

 

[rca]

max cap & max trans involve in the timing (you could see in the liberty table).
the max fanout does not involve and could be ignore if all timing are met.

 

[yadavvlsi]

Max fanout limit is defined to avoid max. cap and max. transition violations as far as you meeting them, you can ignore max. fanout violations.

 

[mask_layout]

Max fanout limit is defined to avoid max. cap and max. transition violations as far as you meeting them, you can ignore max. fanout violations.

yup agree.
Max fanout is used to control number of loads driven by one output,
however the amount of load that can be driven by an output is measured in terms of its load capacitance, thus as long as the capacitive load is lower than is can drive, it should be good ok.

 

[pavanks]

yup agree.
Max fanout is used to control number of loads driven by one output,
however the amount of load that can be driven by an output is measured in terms of its load capacitance, thus as long as the capacitive load is lower than is can drive, it should be good ok.

If max fanout is not required. Then why is it defined in the std lib ?
If we fix all the violations what more can be achieved?

Thanks

 

[cop02ia]

Hi,

Max. fanout is just a "rule of thumb" approach.
As stated by others previously, the max. cap and max. transition violations are the constraints that are measured.

However, to get a feel of how much fixing is needed, the max. fanout can be used.
Furthermore, it helps "balance" the no. of output cells by introducing more levels in the design, e.g. by adding buffers to reduce the fanout.

A cell output port might be able to handle the worst load of 300 input ports, but most designers might want to impose some limit as routing congestion can become an issue.

I'm not sure what more would you want when you have 0 violations.
Perhaps you mean something like better yield?

Best regards,
I-FAB

 

[pavanks]

Hi,

Max. fanout is just a "rule of thumb" approach.
As stated by others previously, the max. cap and max. transition violations are the constraints that are measured.

However, to get a feel of how much fixing is needed, the max. fanout can be used.
Furthermore, it helps "balance" the no. of output cells by introducing more levels in the design, e.g. by adding buffers to reduce the fanout.

A cell output port might be able to handle the worst load of 300 input ports, but most designers might want to impose some limit as routing congestion can become an issue.

I'm not sure what more would you want when you have 0 violations.
Perhaps you mean something like better yield?

Best regards,
I-FAB

"Furthermore, it helps "balance" the no. of output cells by introducing more levels in the design, e.g. by adding buffers to reduce the fanout."

How can adding buffers reduce the fanout?

one more Q
Will the value max fanout be in the std lib file?


Thanks

 

[cop02ia]

Hi,

To clarify, say your port "Y" outputs to 40 MUX inputs - you can add another level of buffers in the design to reduce this fanout of 40.
Suppose you connect port "Y" to 4 new buffers, so, evenly distributed, each buffer will only have to connect to the 10 MUX inputs.
Now we have a fanout of 4 at port "Y", & each of the added buffers will have a fanout of 10.

Max. fanout may not be listed in the library, but the tools should have the option to create it.
Also, you can specify it in your constraint file.

-Best regards,
I-FAB

 

[pavanks]

Hi,

To clarify, say your port "Y" outputs to 40 MUX inputs - you can add another level of buffers in the design to reduce this fanout of 40.
Suppose you connect port "Y" to 4 new buffers, so, evenly distributed, each buffer will only have to connect to the 10 MUX inputs.
Now we have a fanout of 4 at port "Y", & each of the added buffers will have a fanout of 10.

Max. fanout may not be listed in the library, but the tools should have the option to create it.
Also, you can specify it in your constraint file.

-Best regards,
I-FAB

Thanks for the explaining. One last question.
If its not in the lib, how to u specify it? how do u come up with the max fanout value?

 

[cop02ia]

Hi,
Like I mentioned, put it in the SDC constraint files - or use your P&R tool commands.
You should have documentation on that, if not, find them.
Since it's just a guide, the designer will have to come up with a value.
Try 20 fanout first - use trial & error to see the effects.

-Best regards,
I-FAB

 

[pavanks]

Hi,
Like I mentioned, put it in the SDC constraint files - or use your P&R tool commands.
You should have documentation on that, if not, find them.
Since it's just a guide, the designer will have to come up with a value.
Try 20 fanout first - use trial & error to see the effects.

-Best regards,
I-FAB

"Try 20 fanout first - use trial & error to see the effects."
Should we check for effects in timing and congestion ?
Any other effects ?

 

[josesmn]

Hi,

Max. fanout is just a "rule of thumb" approach.
As stated by others previously, the max. cap and max. transition violations are the constraints that are measured.

However, to get a feel of how much fixing is needed, the max. fanout can be used.
Furthermore, it helps "balance" the no. of output cells by introducing more levels in the design, e.g. by adding buffers to reduce the fanout.

A cell output port might be able to handle the worst load of 300 input ports, but most designers might want to impose some limit as routing congestion can become an issue.

I'm not sure what more would you want when you have 0 violations.
Perhaps you mean something like better yield?

Best regards,
I-FAB

Do reducing fanout increase the timing performance of the circuit?

Jose

 

[vijayR15]

Hai everyone:-
Some times the tools cannot fix max fanout violation.. To fix fanout violation, split the maxfanout load by adding buffer.. you can write your own script to fix this..

EX;-
consider you are having a maxfanout of 20 in a cell named "add1" but real maxfanout should be 11.
Then conider output pin of add1 is Y.. Then detach 10 terms attached to add1.. Then attach a buffer to y pin of add1. then connect the detached 10 terms to that buffer. You will not get fanout violation..

For a single path u can do it manually.. But while you are moving forward with more.. You can write your own script to fix this...



Hope so..This may help someone.....:razz:

 

[kambadia]

Hai everyone:-
Some times the tools cannot fix max fanout violation.. To fix fanout violation, split the maxfanout load by adding buffer.. you can write your own script to fix this..

EX;-
consider you are having a maxfanout of 20 in a cell named "add1" but real maxfanout should be 11.
Then conider output pin of add1 is Y.. Then detach 10 terms attached to add1.. Then attach a buffer to y pin of add1. then connect the detached 10 terms to that buffer. You will not get fanout violation..

For a single path u can do it manually.. But while you are moving forward with more.. You can write your own script to fix this...



Hope so..This may help someone.....:razz:

Hi vijay do u have this script....

 

[OhaAmo]

Max fanout can also be important to achieve balanced H-tree, where there are buffers there that might drive tens and maybe hundreds of gate (Clock gating cells and so).
So you should constraint max fanout value to not overload parts of the tree.

 

[vijayR15]

Hai kambadia,

Yes I did a script for fanout fixing in cadence soc encounter