Do the circuit component sizes effect the s-parameters during EM simulation on ADS?

Here is my LNA design at 2.4 GHz below:


When I start to do an EM simulation, what kinds of things should I consider about my 2.4 GHz LNA before starting an EM simulation? I want to get a very accurate answer as it would be when I get it manufactured and tested. I was thinking, would it matter about the size of my resistors, dc-blocking capacitors, dc-feed inductors, and the actual size of the transistors when I layout the circuit on ADS, or does it not consider the size? Cause when I started to do a layout in ADS, Something dawned on me, that maybe the size of the actual components might effect how the s-parameters might come out, also I am using ideal capacitors, inductors, and resistors, would that effect my LNA performance, if so, how can I configure my components to act more realistic to the actual component values in real life? I have placed a picture of a generated layout, but my components are all crunched up in one spot, just showing you this, so you understand what I'm trying to ask.



couple of other random questions for design
Btw, I am considering testing characteristic curves to 4 or 5 ATF55143 transistors on a curve tracer to see which one has a closer resemblance to the bias point that is on my ADS circuit 3V/30mA, when Vgs = 0.5283V... Also, how many vias should i have at the end of a shorted stub, I was thinking at-least 2, since it would decrease idunctive parasitics?

skatefast08 said:

would it matter about the size of my resistors, dc-blocking capacitors, dc-feed inductors, and the actual size of the transistors when I layout the circuit on ADS

Click to expand...

Yes, size matters for RLC, because internal parasitics and resulting self resonance frequency are very different. You can find ADS component libraries on manufacturer webseites, e.g. Murata. There is also an accurate, comprehensive component library by Modelithics (commercial product, license required).

Vias: Two vias side by side can be useful. Two cascaded vias (one behind the other) have little effect because current takes the shortest path.

You're using ideal components which have no layout equivalents.You should download PDK of Passive Devices Manufacturers such as Murata or AVX ( Coilcraft,ATC etc) then you design your layout.
Also, GND symbols cannot be used in layout ( except LVS purposes ) to simulate this layout in EM Simulation Environment.
I recommend you to seek the internet to find some tutorials about how to design a circuit in ADS with layout..

If you're just wondering about if LNA will work, I built Amplifiers with that exact transistor before. Just give it the DC bias it wants; and do the stabilization thing accordingly, and it will work.

If you want to design a "good" LNA, your ADS circuit design needs to look so much detailed. You can start by using more detailed models for inductor/capacitors. Place vias like a madman along the signal path; but don't include them(vias) into EM simulation, it makes things works so much slower.

For a starter, you can simulate a LC or R-L or R-C match wil detailed models; and observe how their respective parasitics make the SRF come out(unlike ideal ones).

--Regarding your question about size of element: Simulate a bias-tee using S-parameters of an actual inductor; instead of putting a dc-feed.