do synthesis tool distinguish which is clk which is rest of a ff?

module which_clock (x,y,q,d);
input x,y,d;
output q;
reg q;
always @ (posedge x or posedge y)
if (x)
q <= 1'b0;
else
q <= d;
endmodule

In this, how does the synthesis tool, figure out which is clock and which is reset. Is the statements within the always block is necessary to find out this or not ?

I think the answer is yes. the synthesis tool should have templets to figure out which one is rest which one is clk. otherwise, it might connect the clk to the rst pin of the fflop.

plz share your idea.

Synthesis tools today can see the posedge statement and take it as a clock by defualt. hence for your code the synthesis tool will I think assign two clock buffers. There might be some option to close this default assignment but I dont exactly know it yet.

bests,
Shan

syedshan said:

Synthesis tools today can see the posedge statement and take it as a clock by defualt. hence for your code the synthesis tool will I think assign two clock buffers. There might be some option to close this default assignment but I dont exactly know it yet.

bests,
Shan

Click to expand...

you said "assign two clock buffers". i don't quit understand this. do you mean if synthesis tool treat it as clk, then it will buffer it by default. I am wondering this because i read some articles and they says don't use data to connect to the clk of fflop because the synthesis tool treat them different. I am wondering whether "treating them differently" means clk signals will be buffered by default.

yes. I mean what you understand

When you put @posedge clk synthesis tools look it as if it is a clock (at least I can assure you about the Xilnx synthesis tool).
Where as what you read in article is right. You should put proper clock to the clk input of the flip-flop. Since there are dedicated clock buffers and paths in the FPGAs which are only dedicated to be low-jitter, low noise which are essential for the clock. Where as the data paths are just normal connecting paths, they do not much emphasis on the jitter control etc.

The software (like plan-ahead) will assign the buffers when assigning the pin locations and defining timing constraints in the constraint file (.ucf file).

But you can also buffer clock signals manually...which FPGA you are using?...like for xilinx fpgas we use following to instantiate the global clock buffer

// BUFG: Global Clock Buffer (source by an internal signal)
// All FPGAs
// Xilinx HDL Libraries Guide, version 11.2
BUFG BUFG_inst (
.O(O), // Clock buffer output
.I(I) // Clock buffer input
);
// End of BUFG_inst instantiation

Click to expand...

Hope this helps

The difference between posedge x and posedge y is unequivocally declared by the if (x) statement. The signal that appears only in a posedge event is the clock. Problems may arise in constructs that con't correspond to the expected template structure. By the way, ambiguity of posedge/negedge is a pure Verilog problem. VHDL has e.g. a different syntax to define a register clock.

According to the template, x is recognized as an asynchronous clear signal. Depending on the source of the signal and the FPGA family design, it might use global clock routing resources, although it's no clock. In FPGA synthesis, a clock buffer primitive represents a global clock network. But the asynchronous clear can be also sourced by local logic. In this case it doesn't use global clock networks or clock buffers.