Do FPGA IO pins need decoupling capacitors?

[hobbskw]

Hello, I have been trying to figure out if I need to put decoupling capacitors next to the IO pins of my FPGA. It is a Zynq 7000. I checked their hardware design guide and couldn't find an answer, as well as several other forums. The Zynq guide says to either place a 4.7 uF within two inches of the edge of the chip, or a 0.47 uF within half an inch. But it doesn't specify which pins these should be linked to. Everyone mentions that power supply pins should have them, like VCC, but no mention of IO pins. I appreciate any help!

Zynq guide I am referring to is here: https://www.xilinx.com/support/documentation/user_guides/ug933-Zynq-7000-PCB.pdf

 

[wwfeldman]

I have never put a decoupling cap on an I/O pin, only on power pins.
I have never heard of anyone using a decoupling cap on an I/O pin.

you do not need decoupling caps on I/O pins, only on power pins.

 

[betwixt]

I would say absolutely DO NOT add them to I/O pins. It slows down logic transitions and increases the current flowing in and out of the pin. Additionally, it can cause problems when the power is turned off and the capacitors start to discharge 'reverse polarity' into the pins, meaning when the pin voltage is higher than VDD/VCC.

Brian.