DNL & INL analysis about ADC

sinewave inl and dnl adc histogram method

I am designing a pipeline ADC and I want to simulate the INL & DNL of the ADC by hspice and matlab. I will highly appreciate you if you can give me some advises about this analysis!!

I used to read an article from Maxim. I have many problems about this article.
1) In the article it suggest us to add a sine signal to the ADC input. How about the relationship between this signal and the clock signal? Is it following the request for fft analysis?
2) Which simulation resultes we need to get for DNL INL analysis? Are we only need the last output of the ADC? Are we need to print results in the .lis file?
3) In this article there is a word I can't understand
"apply a close to full-scale sine wave (but not clipping) and find the mid-code for the applied signal"
what is the mid-code means?

I also read the same question on this board. Maxwellqu suggest that " I guess that the best option is to put a slow ramp at the input and determine the input voltage where each code transition occurs. " how can we get real value of the input voltage where each code transistion occures? Do we need to read the transistant waves of the ADC output or we need to print the result of the transistant analysis to the .lis file and analysis it by Matlab?

Thanks a lot!

inl dnl histogram method slow ramp

Hi,

I've been dealing with the same problem in MATLAB as well, so I thought I'd put in my 2 cents.

First off, the sine wave in comparison with the clock signal. If you're referring to the FFT analysis, it is important that the sine frequency is not a integer multitude of the clock frequency. Also, since the FFT analysis is actually a DFT, dealing with sampled waves, it is important the the sampling is first of all uniform and also not an integer multitude of the sine frequency. Long story, why? If your sampling or clock is an integer multitude of the sine frequency, the sampling points will always hit the sine at the same amplitude. If it is not, the sampling points will always be a bit offset and sample the sine at different point, creating a much denser sampling pattern on the sine (seen over a number of sine periods).

A more practical approach:

Choose sine frequency (say roughly 1M)
Sine_period = 1us

FFT size? Let's say 2^16 = 65536 points
Distribute points along 100 periods or so --> sample_time = 100us/2^16 = 1.525878906250000e-009 corresponding to 655.36MHz (not integer multitude)

Now, the clock can be chosen an integer multitude of the sampe frequency (how cares if you're sampling the clock at the same points within a period) so say you want a 10M clock --> choose 655.36MHz/5 = 13.1072MHz or t_clock = 1/13.1072M.

Simulate 100us, run FFT.

This is a very ellaborate way to do an FFT, but it will provide you with a clean FFT, even without windowing.


Now, on the DNL/INL measurements. Slow is the key here, be it either a ramp or sine wave, DNL/INL measurements are quasi DC. For both measurements you need the input signal. The article you read probably states definitions for DNL and INL, although I've heard different people using different methods to measure it.

I am unclear though on what the FFT should have to do with the DNL and INL measurements.

adc fundamental, inl

Would like to ask if anyone have successfully obtained the INL and DNL using the histogram method by maxim? I'm still unsure how to setup the logic analyzer to obtained the data needed.

sine inl dnl

Hi everyone!

I am still a beginner in Analog design. Explanation by StevenL sparked my interest. I want to add-up something here:

First, to simulate for ADC performance, there are two type; Dynamic range and DC(accuracy).
To simulate for dynamic range, we need to perform FFT analysis. The input is a sinewave with 1kHz (The amplitude is set to be just below the maximum input voltage range) The syntax in HSpice is as follow,

.fft v(output) np=4096 (more detail can be obtained in HSpice manual book)

Then we can determine the dynamic range from the output plot of FFT analysis. For instance, the Spurious Free Dynamic Range is a difference between peak amplitude of fundamental frequency (1kHz in this example) and peak of the first harmonics amplitude. Maxim provides good explanation about this measurement.

Added after 3 minutes:

Now to simulate for DC i.e. INL and DNL.

I came across few notes that we can simulate for INL/DNL using HSpice Monte Carlo analysis. Anyone knows about this?

The other way of doing it is to use matlab.

basic method to determine inl and dnl

For DNL and INL analysis, we follow the DC testing method. I mean we sweep the input DC source over the full scale. Histogram testing method is suitable in MATLAB.