division operation in vhdl

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xilinx1001

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Hi,

I need to use division in vhdl program

I know that I cannot use division symbol directly in vhdl

How can I implement the division operation in vhdl

I need to convert the result of the division operation into BCD

How can I do this

Any suggestions are appreciated
 

What are you trying to divide, signed? unsigned? integer?

Yes, you CAN use "/" in VHDL; whether you can synthesis this depends on your tools. You can also instantiate IP that will perform division.
 

Hi,
Thanks for ur reply
I need to divide two integer values and I need to display the result on 7 segment display
I tried to use "/" but I am getting a error like "No such operands in this context"
I need to write a function for division on my self
Can u please suggest me some method to solve this
 

Can you post your code? And I think (not sure if that's the correct library) that you need to declare the ieee.numeric_std library in your module.
 

im newbie..
here are my code for division.. but its still error..
hope someone may give some idea

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

ENTITY purata IS
PORT
(
a:IN integer RANGE -127 TO 127;
b:IN integer RANGE -127 TO 127;
clk:IN bit;
d : IN integer := 2;
c:OUT integer RANGE -127 TO 127

);
END purata;

ARCHITECTURE purata OF purata IS
BEGIN
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk='1'THEN
c<=(a+b) / d;


end if;
END PROCESS;
END purata;
 

Synthesis tools usually don't support the / operator. With 2 exceptions:

1. Constants.
2. Multiplies of 2 (which is a simple shift)

Search this forum for: "restoring divide"
 
It looks like you might be trying to divide by two? Just shift right.
Click to expand...
The initiation of 'd' with the number 2 is effective for simulation only.
The synthesis tool ignores that and sees 'd' as an input port capable of being dynamically updated in runtime...
 

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