beginner_EDA
Full Member level 4
Hi,
I have a design running at 125 MHz (8ns Pulse) and I do a large number division (125000000/115200) in system Verilog and it consumes 43 LUTs and 130 CARRY8 and have 34.087ns data path delay and that leading to -26.233ns setup timing violation. I would like to do it using dsp/ip core, if it helps to pass timing.
I saw a documentation here:
but I am not sure if it is the write one for this purpose.
I have a design running at 125 MHz (8ns Pulse) and I do a large number division (125000000/115200) in system Verilog and it consumes 43 LUTs and 130 CARRY8 and have 34.087ns data path delay and that leading to -26.233ns setup timing violation. I would like to do it using dsp/ip core, if it helps to pass timing.
I saw a documentation here:
but I am not sure if it is the write one for this purpose.