nanock
Member level 1
- Joined
- Mar 13, 2011
- Messages
- 40
- Helped
- 1
- Reputation
- 2
- Reaction score
- 1
- Trophy points
- 1,288
- Activity points
- 1,564
Hi,
I'm simulating a PLL based frequency synthesizer using dual modulus prescaler. I know I should divide output with MP+A while A is programmable down counter. The theory is "N=A(P+1)+(M-A)P=MP+A". I found a control logic as below to realize this.
My question is how to implement "+A" in divider? I mean I can divide by MP but what about MP+A?
I'm simulating a PLL based frequency synthesizer using dual modulus prescaler. I know I should divide output with MP+A while A is programmable down counter. The theory is "N=A(P+1)+(M-A)P=MP+A". I found a control logic as below to realize this.
My question is how to implement "+A" in divider? I mean I can divide by MP but what about MP+A?
Last edited: