Divide by two counter using D-Latch

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spartanthewarrior

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divide by 2 counter

How can i design divide by two counter using D-Latch
 

design a divide by two counter using d-latch

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d latch

Here is the 'code' for a D-latch.

Note that a D-latch is typically something you DON'T want in a FPGA design.
FPGA designs use clocked latches (flipflops), and not this D-latch type (which is not edge sensitive but level sensitive).

Code: 
  process (c, d)
  begin
    if (c = '1') the
      q <= d;
    end if;
  end process;
 

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