Divide by odd number (for divider in PLL for synthesize freq

[E-goe]

how to design divide by odd number

Hi

I want to design the divide by N-part of a PLL in CMOS. This block has to divide the output freq by an odd number. So I can not just use D-flipflops to do this as this divides the output freq by an even number. Wright?????

So do you know a way to do this? Schematic, papers.... are welcome

Greetz E-goe

 

[Moss]

Re: Divide by odd number (for divider in PLL for synthesize

If you have counter, you need just to connect desired outputs to AND gate. For example for 4 bits counter( with ouputs Q0 to Q3)l with frequency 1/3 from the input( devide by 3). You must connect Q0 and Q1 to AND gate. Output of and is desired frequency. You must keep in mind that in this way duty cycle will not be 50%...