Divide by 40 / 41 with discrete TTL

[fjpompeo]

Need to build a divide by 40/41 with discrete TTL, I mean when an input goes from low to high divide the input frequency by 41 else when it is low divide by 40.

I know that there are ASIC prescalers that works this way but is very difficult to find then.

Regards,

Fernando

 

[IanP]

Division by 40, 41 or, in general, by N, can be realized by CMOS programmable divide-by-N counter - the CD4059 .. for more details see its data sheet ..
**broken link removed**

Regards,
IanP

 

[fjpompeo]

Hi IanP,

Very thank you for your prompt reply. Due to a low speed CMOS is not acceptable to my project so I need TTL LS or F or even ALS so they are very fast parts up to 150MHz I guess.

Regards,

Fernando

 

[artem]

You can realise that by 2 serially connected parallel load decrementing/incrementing couters from series you mentioned or via cpld chip.

 

[svicent]

Divide by 40 & 41 in a PAL16V8:

| PAL16V8
| in: (RST, E), io: Q[5..0], clock: CLK
| register: CLK // Q[5..0]

| Map: Q[5..0] -> Q[5..0]
| {
| n -> 0, RST
| n -> n+1, RST' & (n < 39 + E)
| n -> 0, RST' & (n > 38 + E)
| }


File DIV4041.ZIP contains the complete source code, the jedec file and the simulation results DIV4041.LOG

 

[jonw0224]

You just have to build something like this:

Take the output off the RESET wire.