The background of this question is that we need a differential clock ranging from 100Mhz to 750Mhz with low jiiter(rms jitter is less than 1ps).The ducy cycle is 50%.The ring VCO is easy to cover this range,but the jiitter is too high.So the LC VCO is selected for this application.As you know,the large freq range is a big challenge,but I can try.I think the VCO can oscillate at 2Ghz~3Ghz and then we get the clock by dividing the freq to a low value.
From the data file from FAB,I find the Q of inductors is a bit higher in 2~3Ghz than in other freq range.
In this way,I can get what I want:
VCO freq: 2GHZ---3GHZ;
1/2 freq: 1GHZ-----1.5GHZ
(1/2)*(1/2) freq:0.5GHZ----0.75GHZ
(1/2)*(1/3) freq:0.333GHZ----0.5GHZ
(1/2)*(1/4) freq:0.25GHZ----0.375GHZ
100MHZ~250MHZ is not a problem.
As I know, the div-by-3 and div-by-5 ckts in SCL cannot output a signal with 50% duty cycle.
Is there a better choice for me?
Thanks a lot.