Dithering for fractional-N PLL?

[RickLi]

dithering pll

I am designing a fractional-N PLL, with a MASH 1-1-1 sigma-delta modulator. I simulated the SDM with Matlab, and saw that there were spurs (idle tones) at the output. I added a pseudo-random bit generated by LFSR to the LSB of the SDM input, but the spurs remain. Seems that the dithering doesn't work. Can any one kindly introduce me some reference about dithering? Thanks very much.

 

[xiaorui2007]

dithered pll

I am also confronted with this problem.
when I put signal Xin[k]=0.5+0.25*sina(100*k/pi)
into to MASH 1-1-1 sigma-delta modulator, I can see the noise in low frequency is moved to high frequency. But when I put MASH 1-1-1 sigma-delta modulator in F_N PLL, I don't find it works well, the spur still existent. May onyone knows why? Thanks very much .

 

[RFDave]

dithering fractional pll

SDM's are prone to idle tones when you are using rational numbers as the input value. Try a 6 or 7 digit long random number ( 0.259846) for example. If you are modulating the SDM input, perhap's you are seeing the modulation spectrum at the output.


Dave

 

[RDRyan]

1 lsb initial mash

Why should we use 6 or 7 digit long random number? what is the purpose of using that?

In MIT lecture, the input of MASH 1-1-1 is a sin wave with a DC offset. And I can see the spurs is supressed at low frequency.


Ryan

 

[ieropsaltic]

dither fractional-n

Try using a 20-bit bus for the input and set the 2 LSBs to ones .I tried this once with a MASH-1-1-1 for Fractional N PLL for WiLAN and it worked fine .
The idea is that when you apply a DC input that can be represented as a rational number a/b , after a number of cycles = 2*b if (a+b) is odd or (a+b)/2 if (a+b) is even, the internal states of the accumulators will be the same as the initial conditions and the output will repeat itself causing periodicity thus idle tones .

By setting the LSBs to one , we try to make the repetition period too long that would mitigate the idle tones and would just cause very small DC offset.

To test that using MATLAB, add to the DC input 3/2^21 (assuming that all input values are normalized i.e <1) .

 

[marcel]

fractional n pll

Maybe It can suppress the idle tone better to increase the energy of dither signal. For MASH1-1-1 modulator, the idle tone can also be suppressed by setting correctly the initial value of the first stage accumulator.

Best regards
Marcel