Distance between poly gates in the matched array is different

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Junus2012

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Dear friends,

attached you see please my matched array for the given circuit.

As you can see that in the first array management every transistor was individual and the distance are identical between every gate.
In the second arrangement I merged the shared region to reduce the size of the layout, but as you see that distance are not becoming identical between each transistor in the array.

I don't know if that will effect the matching or not, but I have a feeling that the electrical characteristics of both might be different,

which one should be better ?

Thank you very much
 

Well, in the second arrangement you have two A transistors that are merged and two B transistors, also merged. So, this kind of makes the two rows in this arrangement kind of the same. However, if I have to choose, I'll vote for the first arrangement because there all transistors are under same conditions (provided dummies are used on the sides).
 
Dear Suta,

As you said in the first arranegement with dummy transistors it will be fully symetrical circuiit. while in the second array the internel transistors will be etched differently from the outer een if there are dummuie.

But Suta if I have a bigger arrray of more than two transistor, suppose like ABCD, do you think that if the arrangement led to merge only A and B but not C and D ? soon I will provide you wit such connection to make the case more clear
 

There is also another possibility. Your transistors above as per the schematic don't have common nodes besides the gates. So, at a first glance you can't put them in the same diffusion. However, you can still use same diffusion area for both if you allow for a dummy that is connected across the two branches with gate to gnd - say one terminal of the dummy is connected to the left branch, the other to the right branch and gate to gnd. This way it will separate the transistors that are in the two branches but will give the possibility to use one contiguous diffusion area.
 
Dear Suta,

thank you for this smart idea, I see it is the best to implement, I have plot the circuit connection to be confirmed from you.. the only one thing I didn't simulate this topology so I don't know its impact yet on the circuit performance

Thank you once again



 

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