night cat
Member level 1
Un-believable, but it is true after the measurement !
See attached, it is the rail to rail IN/OUT opamp from SEIKOII.
points are:
1. 0.9V~5.5V working voltage
2. 0.5uA supply current even on 1/2 Vsupply output (unity gain) and even for 5V supply
3. several mA output capability
4. Only one pole for bandwidth response
Any idea to make such ASIC ?
My points are:
1. What process could work as low as 0.9V (0.18u ?) and as high as 5.5V ?
2. How to get so small current source and still can work as low as 0.9V ? (<0.1uA I think for the initial bias current)
3. How does it still be 0.5uA even 5V supply ?
My first question is:
I think it is impossible to get so large resistor (>50M for 5V) by using poly layer in small dice area even the salicide removed.
I tried to use MOSFET to do the simulation by using TSMC 0.18u BSIM3 spice model, L could be as large as 2500u (if W=0.2u).
So that it is impossible to only use one PMOS to do as active resistor.
It is also problem for physical layout (right ?)
I could need to seperate it to many many PMOSs by tying all gates to GND and cascad all D-S. But the minimun working voltage will be increased by lots.
If you can make such OPAMP, then you are the expert !
Any idea ? Interesting !
Welcome to join the discussion !
See attached, it is the rail to rail IN/OUT opamp from SEIKOII.
points are:
1. 0.9V~5.5V working voltage
2. 0.5uA supply current even on 1/2 Vsupply output (unity gain) and even for 5V supply
3. several mA output capability
4. Only one pole for bandwidth response
Any idea to make such ASIC ?
My points are:
1. What process could work as low as 0.9V (0.18u ?) and as high as 5.5V ?
2. How to get so small current source and still can work as low as 0.9V ? (<0.1uA I think for the initial bias current)
3. How does it still be 0.5uA even 5V supply ?
My first question is:
I think it is impossible to get so large resistor (>50M for 5V) by using poly layer in small dice area even the salicide removed.
I tried to use MOSFET to do the simulation by using TSMC 0.18u BSIM3 spice model, L could be as large as 2500u (if W=0.2u).
So that it is impossible to only use one PMOS to do as active resistor.
It is also problem for physical layout (right ?)
I could need to seperate it to many many PMOSs by tying all gates to GND and cascad all D-S. But the minimun working voltage will be increased by lots.
If you can make such OPAMP, then you are the expert !
Any idea ? Interesting !
Welcome to join the discussion !