Disadvantages of pipelining

Hi,
more often then not i end up writing verilog code which doesn't satisfy timing closure due to long combinatorial paths and i invariable introduce pipelining.
i get that it increases latency. are there any other disadvantages of introducing pipelining and what care should be taken while introducing pipeline.


-abhinavpr

There will probably be a tiny increase in resource usage as you increase the amount of registering (and in some cases you may need a bit of logic to handle the data as it passes through, e.g. by generating appropriate valid flags).

However, registers and basic logic are very 'cheap' resources. Therefore, in many high-speed design scenarios (where you are driven by speed), proper pipelining is extremely desirable.

Of course, if your design is not just driven by speed, but also has latency requirements (e.g. in feedback loops with specific loop bandwidth requirements), then at some point you will have to accept a trade-off.

A disadvantage definitely worth mentioning is the time required to write your code. Properly pipelined designs will generally take longer to write. Keeping all your signals properly aligned can take a significant amount of effort and debugging, particularly as your design becomes more complex. For example, whenever you add pipelining stages to one part of a design, you will often need to delay (re-register) various other signals in order to keep them aligned. In some scenarios, this can end up putting constraints on your signals (e.g. "the data inputs must only be valid every 5 or more cycles").

Therefore, if your target clock speed is low (and will definitely stay low), then you may decide pipelining isn't necessary.

Power, area, latency, complexity. (Although not always, sometimes it helps)