Disable Synplify Optimization??

I want to make A chain of inverters which begin and end with dff to make a needed delay in my research. I used libero Soc 10.1 which used Synplify to make its synthesis. The optimization which Synplify made remove my chain and replace it by 1 inverter (When the number of inverters is odd) or no inverter (When the number of inverters is even). Can anyone help me to fix it please?

Thanks

add attribute to preserved these std cells.

I used syn_keep and syn_preserve but it doesn't work. syn_keep used to save combination cells and syn_preserve used to save sequential cells. my circuit is mix between combination and sequential cells. can you tell me how to used them.

here is the code:

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-- Company: <Name>
--
-- File: Chain_Inv.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <Description here>
--
-- Targeted device: <Family:roASIC3> <Die::A3P125> <Package::208 PQFP>
-- Author: <Name>
--
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library proasic3;
use proasic3.all;
library synplify;
use synplify.attributes.all;

entity series_inv is
generic (N : integer := 200);
port (
A : in std_logic;
clk : in std_logic;
reset : in std_logic;
B : out std_logic
);
end series_inv;

architecture rtl_series_inv of series_inv is

signal tmp : std_logic_vector(29 downto 0);
signal A_sig,B_sig : std_logic;

attribute syn_keep : boolean;
attribute syn_keep of tmp: signal is true;

begin

process(clk,reset)
begin
if reset = '1' then
B <= '0';
A_sig <= '0';
elsif rising_edge(clk) then
B <= B_sig;
A_sig <= A;
end if;
end process;

tmp(0) <= not(A_sig);
tmp(1) <= not tmp(0);
tmp(2) <= not tmp(1);
tmp(3) <= not tmp(2);
tmp(4) <= not tmp(3);
tmp(5) <= not tmp(4);
tmp(6) <= not tmp(5);
tmp(7) <= not tmp(6);
tmp(8) <= not tmp(7);
tmp(9) <= not tmp(8);
tmp(10) <= not tmp(9);
tmp(11) <= not tmp(10);
tmp(12) <= not tmp(11);
tmp(13) <= not tmp(12);
tmp(14) <= not tmp(13);
tmp(15) <= not tmp(14);
tmp(16) <= not tmp(15);
tmp(17) <= not tmp(16);
tmp(18) <= not tmp(17);
tmp(19) <= not tmp(18);
tmp(20) <= not tmp(19);
tmp(21) <= not tmp(20);
tmp(22) <= not tmp(21);
tmp(23) <= not tmp(22);
tmp(24) <= not tmp(23);
tmp(25) <= not tmp(24);
tmp(26) <= not tmp(25);
tmp(27) <= not tmp(26);
tmp(28) <= not tmp(27);
tmp(29) <= not tmp(28);

B_sig <= tmp(29);


end rtl_series_inv;

you must instantiate the std cell in the RTL code to be able to apply the constraints to preserved this cell.
the actual code will be reduced by the synthesis tool as you already seen.

it is worked at the synthesis level but the layout doesn't contain that chain. What should I do?

you can modify your RTL , use cells instead of behavioral code , and then specify in your flow those cells as don't touch type of cells. Tool will not look at those cells and will not optimize the logic.

Rahul J