Directory structure for ASIC design

[ecse]

Hi, Folks

Is there any good suggestion or template for Directory structure for ASIC design?

thx in advance
ecse

 

[the_penetrator]

find at opencores.org their recommendation on directory structure

 

[philewar]

In RMM, there is some paragraphs discussing this topic.

 

[crystal]

Typically, directory structures would be :
-source - source files (Verilog/VHDL)
-reports - reports on timing/area/constraints
-scripts - useful tcl scripts
-libs - libraries needed
-mapped - gate-level netlist which has been mapped

These are just some suggestions based on experience. Hope it's useful.

 

[atremp]

you will find some advices from sold

for example:

DC user guide ch 3

 

[satya]

HI u can have the directory structure like this,
------------------proj-------------
|
|-------<PROJ CODE>
|
---------docs
---------netlist
---------rtl
---------sim
---------synth ------|<scr>|
|<reports>|
|<db>|
---------tb ( testbenches)
---------sdf (timing simulation)
--------- test
--------- make
---------sta
---------release

Hope this helps,
Regards,
- satya

 

[maniasonic]

any body has good idea on version control? anyway a dir structure is easier to determine...