As far as I know. Lock time only applies if you are using a PLL. The DDS by design does not have a lock time. The time it needs to change the frequency is just the time to update the phase increment register. Which is added to the phase accumulator on each clock pulse. Frequency changes immediately . Some DDSs update this register on the overflow of the phase register, that is, at the start of a new cycle. The ad9915 seems to have another delay as a result of its pipeline architecture. But it will not change frequency gradually as a PLL would do.