ali ghafoor
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i want some help about SFDR of DDS. how does phase noise of reference CLOCK affect the SFDR of DDS? would SFDR be same or different in following two cases:
1- if i use a clock source of 100MHz and use internal PLL of DDS to make the system reference clock equal to 1GHz(multiplier of 10). clock source phase noise is -140dBc/Hz @ 100kHz offset(after multiplication it will become -140+20log(10)=-120dBc/Hz)
2- if i use a clock source of 1GHz and bypass internal PLL of DDS. clock source phase noise is -120dBc/Hz @ 100kHz offset
would bypassing internal PLL of DDS improve SFDR of DDS (even if the ultimate phase noise of reference clock is same)??
1- if i use a clock source of 100MHz and use internal PLL of DDS to make the system reference clock equal to 1GHz(multiplier of 10). clock source phase noise is -140dBc/Hz @ 100kHz offset(after multiplication it will become -140+20log(10)=-120dBc/Hz)
2- if i use a clock source of 1GHz and bypass internal PLL of DDS. clock source phase noise is -120dBc/Hz @ 100kHz offset
would bypassing internal PLL of DDS improve SFDR of DDS (even if the ultimate phase noise of reference clock is same)??