nanock
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Hi,
I implemented a integer-N pll based frequency synthesizer but it takes 2m second to lock at desired frequency. But my adviser didn't accept it.
Now I want to use DDFS but my project's details are as below:
1- output frequency between 880 MHz and 912 MHz
2- reference frequency 880 MHz or 900 MHz
3- step size 125 KHz
And the question is how can implement 125 khz?
thanks
I implemented a integer-N pll based frequency synthesizer but it takes 2m second to lock at desired frequency. But my adviser didn't accept it.
Now I want to use DDFS but my project's details are as below:
1- output frequency between 880 MHz and 912 MHz
2- reference frequency 880 MHz or 900 MHz
3- step size 125 KHz
And the question is how can implement 125 khz?
thanks