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Dilemna with cadence simulation ????

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nsharma10

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Hello all,

I have noticed a strange thing during cadence simulation and the case is very simple.

The schematic is a 50 ohm source(i.e. port from analogLib) driving a 50 ohm load. IF I do a pss simulation and check the power at the port it is same as the input power that I put in the load.

But if the load impedance is less than 50 then the power shown on the source is low and more surprisingly when the load>50 then the power on the port is great than what I configure in the port.

I am not able to understand this. Anybody has some inputs on it???

Thanks
neel
 

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