digital sine signal generator using DAC and lookup table

it’s not just a function of your DAC resolution. Whats your output frequency? What’s your DAC‘s sampling rate limit? How accurate does your sine need to be? Whats your sampling clock frequency? What’s the application?

Dear Barry

Thank you very much for your response,
you have asked very interested question and indeed I need to cover them all, one by one
So at this stage I wnt to know the optimum number of samples for 10 bit DAC.

Since the output frequency will be changed by the varying the sampling frequency, and this would be my next round of the post to clear it as well as you also suggested.

Therefore for for the moment suppose an ideal case where my DAC has no sample rate limit

Thank you

Hi,

I wanted to ask exactly the same..

Generally speaking neither the DAC, nor the sample rate nor the oversampling rate gives the limits.
You need a so called analog reconstruction filter. It has big impact on the overall performance.

I assume you want a fixed samplig rate.
But is the output signal frequency also fixed? Or does it vary? In which range?

Klaus

added:
So my assumtion was not correct.
I don´t recommend a variable sampling rate, because this means the analog reconstruction filter needs to vary, the same way.

Did you read how DDS works?

Is your output waveform pure sine only? Never want something different?

i did this about 25 years ago for a 60Hz sin wave.
i used an 8 bit synchronous counter to provide addresses to an 8 bit memory to provide data to an 8 bit DAC.
256 steps for a half sine. The second half was handled by a bridge to flip the current direction.
Set the clock frequency at 256 x 60 and away we go.

today, i might use a microprocessor with a built in DAC, same functionality, 1 component.

without any information about what you want this gadget to do, beyond generate sin waves, there is really nothing that can be done to help you, exccept ask questions, and that's been done

Dear Kalus

Thank you for your useful contribution,

You very right, I am considering variable sampling rate, I already have implemented tunable second/4th order low pass filter. A simple test proved the concept and I could have nice and smooth sine signal output.

I used in my design 31 points, which reflects to oversample ratio of 31 I gues. I saved these points in a simple CMOS ROM circuit and pushing the data sequentially using ring counter operated by the clock frequency.

My team leader proposed me this methos because it is easier to implement it than complex DDS (for example AD9833 from analog devices), the thing we want it to design the sine signal generator in our ASIC chip.

My work need a sine signal that required for impedance spectroscopy measurement.

Regards

Thank you very much wwfeldman,

but 256 isn't too much?, it means 512 step you need to fully construct your signal which is difficult for my case since I need to generate at lease up to 3 MHz sine signal. Hence I need to reduce the number of points which will bring me back to my question, what is the optimum value of the number of points to work with 10 bits DAC.

Any way you have presented an interesting point about generating half signal and using bridge to reverse the direction of the currents, do you have any resources about it so I can explore it further?

Hi,

implementing DDS into an ASIC should be an easy task. And I guess it already has been done many times before.
With fixed sampling rate and fixed analog filter.

Still we miss the requirements / specifications.

Klaus

KlausST said:

Hi,

implementing DDS into an ASIC should be an easy task. And I guess it already has been done many times before.
With fixed sampling rate and fixed analog filter.

Still we miss the requirements / specifications.

Klaus

Click to expand...

It will be nice and helpful if you support me with some references where I can start from it.

My singnal specification is have variable sine frequency range from several 10 Hz to 5 MHz. The circuit will be implemented using 0.35 µm technology and the application is for impedance spectroscopy and for general test signal stimula

Hi,

in post#4 I asked some questions. Never been answered.

I still recommend to read how DDS works. There are documents, videos, and even IP for ASICs.


As far as I understand your application: DDS is the way to go.

Klaus

KlausST said:

Hi,

in post#4 I asked some questions. Never been answered.

I still recommend to read how DDS works. There are documents, videos, and even IP for ASICs.


As far as I understand your application: DDS is the way to go.

Klaus

Click to expand...

I agree, even without knowing what the OP really has in mind. And a DDS does not (generally) change the sampling frequency to change the output frequency; it changes the phase step.

This might be helpful -



Regards, Dana.

Dear All,

Thank you one by one for your answers and help with the useful information and links you provided me.

I understood from the most of your comments that DDS is the better choice since it requires fixed sample rate, but can not understand why it needs a fixed filter design as Klaus suggested. How can a filter with a certain cutoff frequency let say 5MHz sommth equaly the generated signals at low frequency or high frequency? that will be interested to know


In the other side my teamleader is decided for the lookup table method and he wants me to continue on it. I have indeed mentioned the required specifications to have frequency range from low tens Hz up to 3 to 5 MHz.
My task is to choose the approporiate number of samples to have better THD as possible with the use of the 10 but DAC we already have.

Dana has shared a link where it shows a negligible gain in THD when moving above 32 samples.

What I need is a scientific relationship theory that describes the limits of sample points on the THD or non-linearity distortion for a given DAC resolution.

Let me present it different way, suppose I go extremely to have 1024 sample, regardless the memory or hardware constraint, may be this number of samples is just a waste because the non-linearity distortion will be dominated by the DAC resolution. Nevertheless, if I use higher DAC resolution of 16 bit then might be this number of sampling is useful.

So I want please to clarify this relationship between the resolution and the number of maximum samples

Then for sure I have still many practical considerations which I want to discuss it afterthen

Thank you once again for your help

Hi,

Junus2012 said:

How can a filter with a certain cutoff frequency let say 5MHz sommth equaly the generated signals at low frequency or high frequency? that will be interested to know

Click to expand...

One applicaton for very low THD and a wide range of frequency is (digital) audio. They did the theory and they deigned filters and so on. Good quality audio DACs (including filters) do this almost perfectly.

One fixed filter, one fixed sampling frequency but a big mixture of random audio frequencies.
About 10 octaves of bandwidth.
And another problem of audio: the huge dynamics in volume.
A CD is designed for 44100Hz sampling rate and 16 bits linear resolution. If you listen to veryquiet music you may go down -60dB of maximum level. This means the signal does not use 16bits anymore, but only 6 bits. Still it´s quite good quality.

***
The DAC output filter is a so called "reconstruction filter". It is designed to most perfectly reconstruct the waveform of the original analog sound.
It´s not a simple low pass filter. It´s a sin(x)/x filter. Indeed just a very good approximation, because the filter can not be designed perfectly, neither analog, nor digital. But they uses some digital filters in combination with output oversampling and - rather simple - analog filters.

***
But for sure an analog filter has it´s limits. When you have a detailed look to a rather low frequency sine wave you will see some "staircases". But if you do the distortion measurement, then the THD is still rather good.

***
How many table entries for a 10 bit DAC?
Honestly I don´t know.
I guess worst case is a "sine" just with 2 entries. Basically the DAC output is a square wave, then.
So without filter you may say a square wave is a sinewave with about 45% THD
use an almost perfect 1st order filter and get 17% distortion
2nd order ... about 8%
...

The critical problem is the first harmonic (3 x fundamental)
If you use more table entries you shift the overtone into higher frequencies and the same time you reduce the amplitude of the overtone. Additionally the filter has higher attenuation at higher frequencies.
So we have three factors that improve the THD.
So I won´t be surprised if the THD goes down with the power of 3 with increasing number of table entires.
(indeed I expect something between the power of 2 ... the power of 3)
So 32 entries are 16 times 2 entries. maybe the THD goes down (becomes divided) by 256 or higher.
I expect it should be quite easy to go below 0.1% THD with 32 entires and a (non perfect ) 2nd order filter.

Still you have to consider the THD of the digital table content of each overtone ... and how much the analog filter indvidually supresses each overtone.

***
Once I´ve generated a 1MHz sine with a 4 bit DAC (indeed 4 CMOS switches) controlled by an FPGA with simple 2nd order RC and a THD of about 0.1% .. used for a high precision LCR meter down to the femto-Farads. Still low cost but rather high mathematics effort. The better you know your target and the better you know your "enemies" the better you can optimize. Thus I always ask for requirements and specifications.

Klaus

What I need is a scientific relationship theory that describes the limits of sample points on the THD or non-linearity distortion for a given DAC resolution.

Click to expand...

Back awhile I saw a reference to an IEEE paper where some rugged mathematician had worked
this out, but not having an IEEE membership was not able to find it in public domain. You might
try to find it with Google ......


Regards, Dana.

I think Anne van der Bosch was Working On it 20 years ago and find relationship between INL and SFDR for current steering DACs. There should be a few papers on it

The question that seems to emerge is, How to get the most utilization out of your 10-bit DAC? Rather than settle for a lesser number of bits?

Falstad's latest version of his simulator now contains ADC & DAC devices.
Free to use and download:

falstad.com/circuit

1) Feed a 1 Hz sine wave to the ADC, taking a sample each fraction of a second. (Or many samples for the duration the sampling window is kept open, to observe operation in theory.)

2) An equivalent binary pattern appears at the 10 outputs (green wires are On).

3) DAC translates the binary number back to a volt level.

Suppose we sample at 50 times initial frequency...
Then values obviously change a large amount from each sample to the next. (The animated simulation shows the wires turning On and Off rapidly as the binary number changes many times.)
Hence we see that a low sample rate fails to take advantage of the resolution available from a 10-bit sytem.
So we need to take samples at hundreds or thousands times initials frequency, in order to fully take advantage of that number of bits.

Hi,

if you want to match with the slope of a sine shape:
We know the max slope is "1" for a sine with an amplitude of 1 .. with a full wave of 2 x Pi.
Example for a 10 bit ADC, the max amplitude is 9 bit or 512.
thus the slope is 512 LSB x 2 x Pi x frequency
so you need a sampling rate of 2^(N_ADC) x Pi x sine_frequency ... to be able to track every single LSB.
Makes a sampling rate of about 30 GHz for 12 bit DAC and 5MHz sine
This is overkill.

Nyquist is the extreme to the other side.
Digital audio was designed for a upper frequency of close to 20kHz with a sampling rate of 44.1kHz.
Just a bit more than 2 samples per sine.
And it just depends on the analog filter if you get 45% THD or less than 1% THD (mind: for the same digital pattern)

Klaus

Dear Friends,

Thank you very much for your explanation, you made it clear for me, I am grateful to you all for your efforts.

So the issue of sampling frequency is solved for me and I will go further for the practical consideration of the DAC itself.

My current problem is that the generated sine signal is suffering the slew are effect at frequency above 100 KHz, I have analyzed that, and according to me it is because the DAC has an output resistorbecause I am using voltage mode DAC. So this resistor together with the load capacitance create an RC circuit and hence time constraint is here depending on the RC value.

Do you have any suggestion to overcome this issue, by the way I am buffering the output using op-amp buffer that has no slew rate limitation to this signal

Thank you
Regards

Hi,

why always that vague? Why don´t you show your schematic, why don´t you say what DAC and OPAMP you use.
Why don´t you say what slew rate you expect and see instead? Scope picture. What resistor, what C?

So we have to ask, can give only vague answers, maybe our answers don´t even fit to your problem.
So it takes long time for you to get a suitable solution. We already are at post#19 ...

***
regarding slew rate and RC:
* Either reduce the value of the R or short circuit it at all
* or reduce or omit the C.

Indeed you need an output filter as already mentioned. It´s the function of a low pass filter to limit/ reduce the slew rate.
You said you use already have implemented a tunable filter, so tune it to get the expected output waveform.

regarding OPAMP:
* every OPAMP has a limited slew rate.

Klaus

There are dacs out there whose FS setltling time at 12 or more bits much
faster. Or use a current dac, typically faster as well for same resoultion.

Even embedded dacs on some ARM processors can do 1 Mhz, FS settling time
to 1/2 LSB of 125 nS......8 bit.


Regards, Dana.