New release at JYE Tech. DSO082 with 10MHz (actually wider) analog bandwidth and 50Msps real-time sampling rate. 10mV/DIV sensitivity, 1024-point FFT, USB connection, and more. Please see:
Why is sdram preferred to buffer data instead of fifo buffer?More complicated (You have to code address too with sd ram).
I'm planning to use this fifo: CY7C4251-15AXC - 8k x 9 CY7C4251-15AXC datasheet pdf datenblatt - Cypress Semiconductor - 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs ::: ALLDATASHEET :::
It's cheap (approx. $6) and maximum frequency is 66 Mhz.
Would it be good with a CPLD?I would choose XC2C64 CoolRunner-II CPLD
It also not too expensive.
I really don't know how to program it.I have to ask some help.
I think if I draw the schematics of the logic in the Xilinx software with the corresponding pins, and then program the chip, I've connected the ADC with the fifo.Am I right? :razz:
The 8k*9 capacity for me I think will be enough.
About access pattern: why whould be pratical a more complex readout than the FIFO's?(maybe faster readout?The goal was a possible slower readout because of the low bandwidth PC connection)
About access pattern: why whould be pratical a more complex readout than the FIFO's?(maybe faster readout?The goal was a possible slower readout because of the low bandwidth PC connection)
You tell me I am not the one implementing a DSO. All I am pointing out is that a FIFO is a lot more restricted than a random access memory.
But basically, large capacity DRAMs are a cheap commodity item. So if you want a large capture buffer that's the way to go. If you settle for 9k*8, then things become a lot simpler. It all depends on what sampling rate + buffer depth you want.
Suppose I use Cypress CY7C68013 running at 480Mbit /s for 2 channel at 8 bit wide each ( storage depth at 4k ) to PC , what is the max sampling rate of ADC ????